SynarioÆs Engineering Capture System (ECS) for system and board design allows designers to develop and manage board projects of growing complexities. As an individual contributor or manager of a design team, you can define and manage your overall board specification and design implementation with hierarchical modules. SynarioÆs ECS has been developed to allow you to leverage the design methods that best meet your needs, and to support top-down design techniques that are increasingly required to shorten design cycles.

In starting a new board project, you can start by defining a top-level block diagram and gather any existing source files that you may want to reuse or modify such as schematics, HDL source files, and related documentation. You may also want to set up your library structure and create a library specific to your boardÆs application.

The Synario ECS environment provides complete support for top-down hierarchical methods that better support increased design complexity, or traditional schematic-based design. Starting from a top-level schematic, you can decompose your design into more detailed schematics or sub- modules. This simplifies design management tasks and allows you to review all levels of your design hierarchy. Synario automates consistency and design rule checking by building an online connectivity database that ensures the integrity of your entire design. You can also verify the functionality between your sub-modules by using HDL-based simulator like our 1076-1993/1164 VHDL Simulator, or an OVI Compliant Verilog Simulator. By identifying connectivity and functional discrepancies at each stage of the board projectÆs implementation, your opportunity for first time success increases, while reducing your number of design iterations. To prepare your design for layout, ECS updates all schematic files and generates a bill of materials for your targeted PCB layout tool. Synario also offers support for your analog circuitry with SPICE netlisting capability.

Once satisfied with your designÆs functionality, SynarioÆs built-in netlisters allow you to interface to EDIF, or your favorite PCB layout tool: AccelÆs Tango, PCAD, or TangoPro; CadenceÆs Allegro; OrCAD®Æs Layout Plus; PADSÆ Perform or PowerPCB; or Zuken Redac's CadStar and RINF formats. When you have completed the physical implementation with your board layout tool, youÆre ready to back-annotate. Synario ECS supports back-annotation of symbol, pin, and net attributes; pin/gate swapping, and reference designators from PCB tools. Enabling you to make changes to your schematic design without having to perform all of your PCB layout processes from scratch.